The Workshop on System-Level Interconnect Prediction is a new forum for the exchange of ideas related to estimation of interconnect design parameters in VLSI CAD applications. All aspects of interconnect design parameter estimations and their applications to CAD and computer architecture evaluation are in the scope of the workshop. This year, special interest goes to Rent's rule. Also, while most research on interconnection length and topology estimations has been performed in the a posteriori (i.e., post-layout) regime, this workshop seeks to promote research on a priori and on-line (i.e., pre-layout and during layout) estimations since these will be fundamental to the development of future convergent design methodologies. Interconnection length estimates also provide deeper insight in the placement properties of circuits on different carriers, e.g. three-dimensional architectures with optical channels used for the third dimension of interconnect.

The 1999 SLIP workshop will provide an informal context for discussions of key new directions in the field, as well as an opportunity to present leading-edge theoretical and experimental contributions. Contributed papers will be printed as unpublished workshop notes, and will also be invited for submission to an edited volume and/or a journal special issue devoted to interconnect parameter estimation in VLSI CAD. Other elements of the workshop include invited presentations that provide attendees with reviews of background and leading-edge research; a tutorial review of Rent's rule and interconnection length estimations will also be organized. Sponsorship by DA-related organizations is anticipated.

Two types of contributions are solicited for the workshop notes:

• position statements, and
  
• complete papers.
  

• Rent's rule and its applications in VLSI CAD
• A priori, on-line, or a posteriori estimation of interconnect design parameters such as interconnection length, area occupancy, signal delay, power dissipation, etc.
• Theoretical estimation techniques
• Estimation algorithms
• Applications of interconnect parameter estimations in CAD, e.g., floorplanning, placement, routing
• Applications of interconnect parameter estimations for system architecture evaluation
• Interconnect parameter estimations for ASIC's, MCM's, and FPGA's

• Submission of complete (camera-ready) papers -- January 25, 1999
• Submission of position statements -- February 1, 1999
• Acceptance notification for complete papers -- February 22, 1999

Anyone seeking to contribute to informal discussions on topics related to the workshop theme may submit a position statement (1 page up to a maximum of 3 pages). The position statements will be used as a basis for round-table discussions.

SUBMISSION OF COMPLETE PAPERS

Authors should submit full-length, original papers (CAMERA-READY, maximum 6 pages double column format, 10pt font) containing

• Title of the paper
• Author names, affiliations, and contact information
• Abstract of at most 200 words
• Paper text

High-quality papers that are concurrently submitted for publication in conferences/journals may be considered by SLIP provided that the concurrent submission is clearly indicated.

SUBMISSION INSTRUCTIONS

To obtain information regarding the Workshop or to be added to the Workshop mailing list, please send e-mail to
dstr@elis.UGent.be
The SLIP web page is at http://www.elis.UGent.be/~dstr/SLIP.html

WORKSHOP ORGANIZATION

WORKSHOP TIP