The Workshop on System-Level Interconnect Prediction is a new forum
for the exchange of ideas related to estimation of
interconnect design parameters in VLSI CAD applications. All
aspects of interconnect design parameter estimations and their
applications to CAD and computer architecture evaluation are in the
scope of the workshop. This year, special interest goes to Rent's rule. Also, while most research on
interconnection length and topology estimations has been performed in
the a posteriori (i.e., post-layout) regime, this workshop seeks to
promote research on a priori and on-line
(i.e., pre-layout and during layout) estimations since these will be
fundamental to the development of future convergent design
methodologies. Interconnection length estimates also provide deeper
insight in the placement properties of circuits on different carriers,
e.g. three-dimensional architectures with optical channels used for
the third dimension of interconnect.
The 1999 SLIP workshop will provide an informal
context for discussions of key new directions in the field, as
well as an opportunity to present leading-edge
theoretical and experimental contributions. Contributed papers
will be printed as unpublished workshop notes, and will also be
invited for submission to an edited volume and/or a journal special
issue devoted to interconnect parameter estimation in VLSI CAD. Other
elements of the workshop include invited
presentations that provide attendees with reviews of background
and leading-edge research; a tutorial
review of Rent's rule and interconnection length estimations will also
be organized. Sponsorship by DA-related organizations is
anticipated.