With physical feature sizes in VLSI designs decreasing rapidly, the
time delay of electrical signals travelling in the interconnect is
approaching and even surpassing the delay through the devices and
gates. The estimation of the interconnect parameters (e.g.,
interconnection length) early in the design cycle therefore gains
importance as an aid for floorplanning, placement, and routing tools.
While most research on interconnect parameter estimations has been
performed in the a posteriori (i.e., post-layout) regime, this special
issue focuses on a priori and on-line (i.e., pre-layout and during
layout) estimations.
This special issue is dedicated to all aspects of interconnect design
parameter estimations and their applications to CAD and computer
architecture evaluation. Special interest goes to Rent's rule.
Authors are encouraged to submit high-quality research contributions
that will not require major revisions. Extensions of papers presented
at the first International Workshop on System-Level Interconnect
Prediction (SLIP'99) are welcomed, but work not presented at the
workshop is also encouraged.
Both regular papers (8 pages in final version format) and short papers
(4 pages) will be considered. The Guest Editors for the Special Issue
are as follows:
| Dr. Dirk Stroobandt | Prof. Andrew B. Kahng |
| University of Ghent, Belgium | University of California at Los Angeles |
| Dept. of Electronics and Information Systems | Computer Science Department |
| Sint-Pietersnieuwstraat 41 | 3713 Boelter Hall, Box 951596 |
| B-9000 Gent, BELGIUM | Los Angeles, CA 90095-1596, USA |
| Tel.: +32 9 264.34.01 | Tel.: +1 310 206.7073 |
| Fax: +32 9 264.35.94 | Fax: +1 310 825.7578 |
| E-mail: dstr@elis.UGent.be | E-mail: abk@cs.ucla.edu |