Being able to model the behavior of interconnections for very small
dimensions and very large operating frequencies is mandatory for
resolving the most critical interconnect-related design
problems. Prediction of system properties as early as possible in the
design cycle is becoming key for preventing layout iterations and the
amount of ``uncertainty'' in the design convergence. This special
issue focuses on system-level predictions and a priori and on-line
(i.e., pre-layout and during layout) estimations of interconnect
related design parameters and characteristics (delay, power, wiring
layers, ...). It intends to build upon the research work to be
presented in the T-VLSI Special Issue
on System-Level Interconnect Prediction that will be published in
December 2000. Authors are encouraged to submit high-quality
research contributions that will not require major
revisions. Extensions of papers presented at the International Workshop on
System-Level Interconnect Prediction (SLIP 2000) are welcomed, but
work not presented at the workshop is also encouraged.
Both regular papers and short papers will be considered. The Guest
Editor for the Special Issue is:
Dr. Dirk Stroobandt
Ghent University, Belgium
Dept. of Electronics and Information Systems
Sint-Pietersnieuwstraat 41
B-9000 Gent, BELGIUM
Tel.: +32 9 264.34.01
Fax: +32 9 264.35.94
E-mail: dstr@elis.UGent.be
All manuscripts are subject to standard T-VLSI review. Prospective
authors should submit their manuscripts electronically to the TVLSI Web
site and indicate that they wish to be considered for this special
issue by adding the keywords "slip: System level
interconnect".
Please also send an E-mail to Dirk Stroobandt notifying him of
your submission.
More information can be obtained from http://www.elis.UGent.be/~dstr/TVLSI2001.html. Alternatively,
you can contact Dirk
Stroobandt for further questions.