Welcome to my website. Since October 2006 I'm a postdoctoral researcher at Ghent University.
My research interests include: computer architecture, design space exploration, multicore systems, reliability, and speculation
techniques like branch prediction, value prediction, return address prediction,...
The 2nd HiPEAC Workshop on Design for Reliability, Pisa, Italy, January 24, 2010: paper submission deadline November 15th, 2009.
Paper "Protecting Prediction Arrays against Faults" by Yiannakis Sazeides, Constantinos Kourouyiannis, Nikolas Ladas and Veerle Desmet; SELSE, IEEE Workshop on Silicon Errors in Logic - System Effects to be held at Stanford University, March 25th, 2009.
Paper "ArchExplorer.org: Joint Compiler/Hardware Exploration for Fair Comparison of Architectures" by Veerle Desmet, Sylvain Girbal, and Olivier Temam; INTERACT-13, Workshop on Interaction Between Compilers and Computer Architecture, held in conjunction with HPCA-15, February 15, 2009.
I received my PhD in Computer Science Engineering from Ghent University in 2006. My advisor was Koen De Bosschere and my PhD was titled ''On the systematic Design of Cost-Effective Branch Prediction''. I was a finalist in the 1st Journal of Instruction-Level Parallelism Championship Branch Prediction in 2004. In 2005 I spend 3 months visiting the Computer Architecture Research Group supervised by Yiannakis Sazeides at the University of Cyprus.
Workshop on Design for Reliability (DFR’09) co-located with HiPEAC-2009, January 25-28 2009
Workshop on Dependable Architectures (WDA) co-located with MICRO-41, November 2008
The 2nd JILP Championship Branch Prediction (CBP-2) co-located with MICRO-39, December 2006
Veerle moved to IWT (LinkedIn page: http://www.linkedin.com/pub/veerle-desmet/6/2a/224)
Last update: November 6th, 2009