Craig Truett Moore, Wim Meeus, Harald Devos and Dirk StroobandtDeveloping memory templates for high level synthesis compilers Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts, pp. 97-100 (2010)
Craig Truett Moore, Wim Meeus, Harald Devos and Dirk StroobandtA parallel for loop memory template for a high level synthesis compiler Digital System Design, 13th Euromicro conference, Proceedings, pp. 449-455 (2010)
Harald Devos, Wim Meeus and Dirk StroobandtTowards a tighter integration of generated and custom-made hardware LECTURE NOTES IN COMPUTER SCIENCE, Vol. 5992, pp. 426-434 (2010)
Craig Truett Moore, Harald Devos and Dirk StroobandtOptimizing the FPGA memory design for a Sobel edge detector Engineering of Reconfigurable Systems and Algorithms, Proceedings, pp. 299-300 (2009)
Harald DevosLoop Transformations for the Optimized Generation of Reconfigurable Hardware Design, Automation and Test in Europe; EDAA PhD Forum, pp. 1-1 (poster) (2009)
Tom Degryse, Karel Bruneel, Harald Devos and Dirk StroobandtLoop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs, pp. 133-138 (2008)
Tom Degryse, Karel Bruneel, Harald Devos and Dirk StroobandtReducing the dynamic FPGA reconfiguration overhead with loop transformations Fourth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, pp. 219-222 (2008)
Harald Devos and Dirk StroobandtHigh-level Synthesis for Data-intensive Applications DAC Workshop: High-level Synthesis: Back to the Future?, pp. 1-1 (CD-ROM) (2008)
Tom Degryse, Harald Devos and Dirk StroobandtFPGA Resource Estimation for Loop Controllers Proceedings of the 6th Workshop on Optimizations for DSP and Embedded Systems (ODES-6), pp. 9-15 (2008)
Harald Devos, Jan Van Campenhout and Dirk StroobandtBuilding an Application-specific Memory Hierarchy on FPGA Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing, pp. 53-62 (2008)
Fabian Diet, Erik D`Hollander, Kristof Beyls and Harald DevosEmbedding smart buffers for window operations in a stream-oriented C-to-VHDL compiler. Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, pp. 142-147 (2008)
Tom Degryse, Harald Devos and Dirk StroobandtLoop Controller Area Estimation for Automatic Design Space Exploration Proceedings of the 18th Annual ProRISC Workshop, pp. 292-297 (2007)
Tom Degryse, Harald Devos and Dirk StroobandtLoop Controller Area Estimation for Automatic Design Space Exploration Architecture and Compilers for Embedded Systems (ACES 2007), pp. 31-34 (2007)
Hendrik Eeckhaut, Harald Devos and Dirk StroobandtThe Energy Scalability of Wavelet-based, Scalable Video Decoding Power and Timing Modeling, Optimization and Simulation (Patmos 2007), Vol. 4644, pp. 363--372 (2007)
Harald Devos, Dirk Stroobandt and Jan Van CampenhoutLoop transformations for generating scalable hardware Design, Automation and Test in Europe; Fourth EDAA Ph.D. Forum, pp. op CD (2006)
Harald DevosLoop transformations for generating scalable hardware Sixth FirW PhD Symposium, pp. On CD (2005)
Hendrik Eeckhaut, Mark Christiaens, Harald Devos and Dirk StroobandtImplementing a Hardware-Friendly Wavelet Entropy Codec for Scalable Video Proceedings of SPIE: Wavelet Applications in Industrial Processing III, Vol. 6001, pp. 169-179 (2005)
Hendrik Eeckhaut, Dirk Stroobandt, Harald Devos and Mark ChristiaensModeling Subbands of a Wavelet Based Scalable Video Codec Proceedings of the 9th WSEAS International CSCC Multiconference: Circuits `05, Systems `05, Computers `05, Communications `05, Vol. 9, pp. (2005)
J. De Maeyer, H. Devos, W. Meeus, P. Verplaetse and D. StroobandtHardware Implementation of an EAN-13 Bar Code Decoder Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 583-584 (2003)
H. Devos, J. Dambre, W. Meeus, D. Stroobandt and J. Van CampenhoutAn exploration of synchronization solutions for parallel short-range optical interconnect in mesochronous systems Proceedings of SPIE: VCSELs and Optical Interconnects, Vol. 4942, pp. 258-268 (2002)
Other publications
Harald DevosLoop Transformations for the Optimized Generation of Reconfigurable Hardware (Lustransformaties voor de geoptimaliseerde generatie van herconfigureerbare hardware) Doctoraatsproefschrift Faculteit Ingenieurswetenschappen, Universiteit Gent, pp. (2008)
H. DevosOptische verbindingen: een systematische exploratie van de ontwerpsruimte Afstudeerwerk FTW, RUG, pp. (2002)
H. DevosProgrammeeromgeving ter ondersteuning van een gedragingsgeorienteerd autonoom systeem Afstudeerwerk FTW, RUG, pp. (1995)