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Fri, 2007-01-12 20:08 — mronsse

Publications of H Vandierendonck

Journal papers

  1. Hans Vandierendonck and Andre Seznec Fairness metrics for multi-threaded processors IEEE COMPUTER ARCHITECTURE LETTERS, Vol. 99(RapidPosts), pp. 4 (2011)
  2. Sean Rul, Hans Vandierendonck and Koen De Bosschere A profile-based tool for finding pipeline parallelism in sequential programs PARALLEL COMPUTING, Vol. 36(9), pp. 531-551 (2010)
  3. Hans Vandierendonck, Sean Rul and Koen De Bosschere Accelerating Multiple Sequence Alignment with the Cell BE Processor COMPUTER JOURNAL, pp. (2009)
  4. Hans Vandierendonck and Andre Seznec Speculative Return Address Stack Management Revisited ACM Transactions on Architecture and Code Optimization, Vol. 5(3), pp. (2008)
  5. Hans Vandierendonck, Veerle Desmet and Koen De Bosschere Behavior-Based Branch Prediction by Dynamically Clustering Branch Instructions Journal of Information Science and Engineering, Vol. 24(3), pp. 919-931 (2008)
  6. Hans Vandierendonck and Andre Seznec Fetch Gating Control through Speculative Instruction Window Weighting Transactions on High-Performance Embedded Architectures and Compilation, Vol. 2(2), pp. 19-39 (2007)
  7. Sean Rul, Hans Vandierendonck and Koen De Bosschere Function level parallelism driven by data dependencies ACM SIGARCH Computer Architecture News, Vol. 35(1), pp. 55-62 (2007)
  8. Veerle Desmet, Hans Vandierendonck and Koen De Bosschere Clustered Indexing for Branch Predictors Microprocessors and Microsystems, Vol. 31(3), pp. 168-177 (2007)
  9. Hans Vandierendonck, Jean-Marie Jacquet, Bavo Nootaert and Koen De Bosschere Formally Modeling Microprocessor Caches and Branch Predictors WSEAS Transactions on Computers, Vol. 5(11), pp. 2588-2595 (2006)
  10. Hans Vandierendonck and Koen De Bosschere XOR-Based Hash Functions IEEE Transactions on Computers, Vol. 54(7), pp. 800-812 (2005)
  11. Veerle Desmet, Hans Vandierendonck and Koen De Bosschere 2FAR: A 2bcgskew Predictor Fused by an Alloyed Redundant History Skewed Perceptron Branch Predictor Journal of Instruction-Level Parallelism. www.jilp.org/vol7., Vol. 7, pp. 1-11 (2005)
  12. Hans Vandierendonck and Koen De Bosschere On generating set index functions for randomized caches COMPUTER JOURNAL, Vol. 47(2), pp. 245-258 (2004)
  13. H. Vandierendonck and K. De Bosschere Randomized Caches for Power-Efficiency IEICE Transactions on Electronics, Vol. E86-C(10), pp. 2137-2144 (2003)
  14. H. Vandierendonck and K. De Bosschere Highly Accurate and Efficient Evaluation of Randomising Set Index Functions Journal of Systems Architecture, Vol. 48(13-15), pp. 429-452 (2003)
  15. L. Eeckhout, H. Vandierendonck and K. De Bosschere Designing Computer Architecture Research Workloads IEEE Computer, Vol. 36(2), pp. 65-71 (2003)
  16. L. Eeckhout, H. Vandierendonck and K. De Bosschere Quantifying the Impact of Input Data Sets on Program Behavior and its Applications Journal of Instruction-Level Parallelism, Vol. 5, pp. 1-33 (2003)
  17. H. Vandierendonck and K. De Bosschere An Address Transformation Combining Block- and Word-Interleaving Computer Architecture Letters, Vol. 1, pp. 14-17 (2002)

Conference publications

  1. Hans Vandierendonck and Koen De Bosschere Whole-array SSA : an intermediate representation of memory for trading-off precision against complexity Proceedings of the workshop on intermediate representations, pp. 69-76 (2011)
  2. Thibault Delavallee, Philippe Manet, Hans Vandierendonck and Jean-Didier Legat Embedding functional simulators in compilers for debugging and profiling Faible Tension Faible Consommation (FTFC - 2011), pp. 55-58 (2011)
  3. Hans Vandierendonck, George Tzenakis and Dimitrios S Nikolopoulos A unified scheduler for recursive and task dataflow parallelism , pp. 11 (2011)
  4. Hans Vandierendonck and Koen De Bosschere Automatic parallelization in the paralax compiler SCOPES '11 : proceedings of the 14th international workshop on software and compilers for embedded systems, pp. 56-63 (2011)
  5. Polyvios Pratikakis, Hans Vandierendonck, Spyros Lyberis and Dimitrios S Nikolopoulos A programming model for deterministic task parallelism MSPC '11 : proceedings of the 2011 ACM SIGPLAN workshop on memory systems performance and correctness, pp. 7-12 (2011)
  6. Hans Vandierendonck, Polyvios Pratikakis and Dimitrios S Nikolopoulos Parallel programming of general-purpose programs using task-based programming models Hot Topics in Parallelism, 3rd USENIX workshop, Proceedings, pp. 6 (2011)
  7. Thibault Delavallee, Philippe Manet, Igor Loiselle, Hans Vandierendonck and Jean-Didier Legat Application-based workload model for wireless sensor node computing platforms Faible Tension Faible Consommation (FTFC - 2011), pp. 35-38 (2011)
  8. Bertrand Rousseau, Philippe Manet, Igor Loiselle, Jean-Didier Legat and Hans Vandierendonck A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010), pp. 273-280 (2010)
  9. Hans Vandierendonck, Sean Rul and Koen De Bosschere The paralax infrastructure : automatic parallelization with a helping hand Parallel Architectures and Compilation Techniques, 19th International Conference, Proceedings, pp. 389-400 (2010)
  10. Hans Vandierendonck and Koen De Bosschere Implicit hints : embedding hint bits in programs without ISA changes Computer Design, IEEE International conference, Proceedings, pp. 6 (2010)
  11. Sean Rul, Hans Vandierendonck, Joris D'Haene and Koen De Bosschere An experimental study on performance portability of OpenCL kernels Application Accelerators in High Performance Computing, 2010 Symposium, Papers, pp. 3 (2010)
  12. Hans Vandierendonck, Sean Rul and Koen De Bosschere Factoring out ordered sections to expose thread-level parallelism PEPSMA 2009 : the 2nd Workshop on Parallel Execution of Sequential Programs on Multicore Architectures, pp. 12-19 (2009)
  13. Sean Rul, Hans Vandierendonck and Koen De Bosschere Can we apply accelerator-cores to control-intensive programs? Application Accelerators in High Performance Computing, 2009 Symposium, Papers, pp. 3 (2009)
  14. Sean Rul, Hans Vandierendonck and Koen De Bosschere Towards automatic program partitioning Proceedings of the 6th ACM conference on Computing frontiers, pp. 89-98 (2009)
  15. Sean Rul, Hans Vandierendonck and Koen De Bosschere A Dynamic Analysis Tool for Finding Coarse-Grain Parallelism 5th HiPEAC Industrial Workshop, pp. 1-2 (Digitaal) (2008)
  16. Hans Vandierendonck and Koen De Bosschere Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses Architecture of Computing Systems - ARCS 2008, Vol. 4937, pp. 261-272 (2008)
  17. Sean Rul, Hans Vandierendonck and Koen De Bosschere Extracting Coarse-Grain Parallelism in General-Purpose Programs Proceedings of the 2008 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 281-282 (2008)
  18. Sean Rul, Hans Vandierendonck and Koen De Bosschere Detecting the Existence of Coarse-Grain Parallelism in General-Purpose Programs Proceedings of the First Workshop on Programmability Issues for Multi-Core Computers, MULTIPROG-1, pp. 1-12 (2008)
  19. Hans Vandierendonck, Sean Rul, Michiel Questier and Koen De Bosschere Experiences with Parallelizing a Bio-informatics Program on the Cell BE Proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, Vol. 4917, pp. 161-175 (2008)
  20. Sean Rul, Hans Vandierendonck and Koen De Bosschere Detection of Coarse-grain Parallelism Architecture And Compilers for Embedded Systems (ACES 2007), pp. 5-8 (2007)
  21. Sean Rul, Hans Vandierendonck and Koen De Bosschere Detection of Function-level Parallelism Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2007), pp. 99-102 (2007)
  22. Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle and Jean-Didier Legat By-Passing the Out-of-Order Execution Pipeline to Increase Energy-Efficiency Proceedings of the 4th international conference on Computing Frontiers, pp. 97--104 (2007)
  23. Hans Vandierendonck and Andre Seznec Fetch Gating Control through Speculative Instruction Window Weighting High Performance Embedded Architectures and Compilers, pp. 120-135 (2007)
  24. B NOOTAERT, Hans Vandierendonck and Koen De Bosschere Conflict Avoiding Caches Invite New Data Layout Optimizations The 10th Workshop on Interaction between Compilers and Computer Architectures, pp. 23-33 (2006)
  25. Sean Rul, Hans Vandierendonck and Koen De Bosschere Function Level Parallelism Driven by Data Dependencies Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP), pp. 8 (2006)
  26. Sean Rul, Hans Vandierendonck and Koen De Bosschere Function Level Parallelism Lead by Data Dependencies 7e Doctoraatssymposium, pp. 97 (2006)
  27. Igor Loiselle, Thibault Delavallee, Philippe Manet, Hans Vandierendonck and Jean-Didier Legat Study of Parallelism between memory accesses for multi-bank architectures Architecture And Compilers for Embedded Systems (ACES 2006), pp. 80-83 (2006)
  28. Sean Rul, Hans Vandierendonck and Koen De Bosschere Function Level Parallelism Lead by Data Dependencies Architecture And Compilers for Embedded Systems (ACES 2006), pp. 76-79 (2006)
  29. Hans Vandierendonck and Koen De Bosschere On the Impact of OS and Linker Effects on Level-2 Cache Performance Proceedings of the International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 87-95 (2006)
  30. Hans Vandierendonck and Pedro Trancoso Building and Validating a Reduced TPC-H Benchmark Proceedings of the International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 383-392 (2006)
  31. Hans Vandierendonck, Jean-Marie Jacquet, Bavo Nootaert and Koen De Bosschere A Formal Model for Microprocessor Caches Proceedings of the 10th WSEAS International Conference on Computers, pp. 1056-1061 (2006)
  32. Sean Rul, Hans Vandierendonck and Koen De Bosschere Classifying Data Dependencies Between Functions Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006), pp. 117-120 (2006)
  33. Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout and David J. Lilja The Exigency of Benchmark and Compiler Drift: Designing Tomorrow`s Processors with Yesterday`s Tools Proceedings of the 2006 International Conference on Supercomputing (ICS), pp. 75--86 (2006)
  34. Hans Vandierendonck, Philippe Manet and Jean-Didier Legat Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses Design, Automation and Test Europe, pp. 357-362 (2006)
  35. Bavo Nootaert, Hans Vandierendonck and Koen De Bosschere The placement of matrices when using XOR-based hashing ACES 05 Symposium Proceedings, pp. 19-20 (2005)
  36. Bavo Nootaert, Hans Vandierendonck and Koen De Bosschere Alignment of matrices when using XOR-based hashing ACACES 2005 Poster abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, pp. 119-122 (2005)
  37. Veerle Desmet, Hans Vandierendonck and Koen De Bosschere Interference in Branch Predictors: A Systematic Approach Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2005), pp. 173-176 (2005)
  38. Hans Vandierendonck and Koen De Bosschere Experiments with Subsetting Benchmark Suites Proceedings of the Seventh Annual IEEE International Workshop on Workload Characterization, pp. 55-62 (2004)
  39. Hans Vandierendonck and Koen De Bosschere Eccentric and fragile benchmarks IEEE International Symposium on Performance Analysis of Systems and Software-ISPASS, pp. 2-11 (2004)
  40. Veerle Desmet, Hans Vandierendonck and Koen De Bosschere A 2bcgskew Predictor Fused by a Redundant History Skewed Perceptron Predictor The 1st JILP Championship Branch Prediction Competition (CBP-1) http://www.jilp.org/cbp/Agenda-and-Results.htm, pp. Internet (2004)
  41. H. Vandierendonck and K. De Bosschere Many Benchmarks Stress the Same Bottlenecks Workshop on Computer Architecture Evaluation Using Commercial Workloads, pp. 57-64 (2004)
  42. H. Vandierendonck and K. De Bosschere On the use of statistical data analysis techniques in workload characterization Fourth FTW PhD Symposium, pp. on CD (2003)
  43. H. Vandierendonck and K. De Bosschere On the use of statistical data analysis techniques in workload characterization 1st Flanders PhD Symposium: Industry-Ready Innovative Research, pp. on CD (2003)
  44. Hans Vandierendonck and Koen De Bosschere Trade-Offs for Skewed-Associative Caches Parallel Computing: Software Technology, Algorithms, Architectures and Applications, Vol. 13, pp. 467-474 (2003)
  45. H. Vandierendonck, H. Logie and K. De Bosschere Trace Substitution Euro-Par 2003 Parallel Processing, Vol. 2790(2790), pp. 556-565 (2003)
  46. B. De Sutter, H. Vandierendonck, B. De Bus and K. De Bosschere On The Side-Effects of Code Abstraction Proceedings of the 2003 ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES`03), pp. 244-253 (2003)
  47. H. Vandierendonck Efficient Evaluation of Randomising Set Index Functions for Cache Memories Program Acceleration through Application and Architecture driven Code Transformations: Symposium Proceedings, pp. 27-30 (2002)
  48. L. Eeckhout, H. Vandierendonck and K. De Bosschere Workload Design: Selecting Representative Program-Input Pairs Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques, pp. 83-94 (2002)
  49. H. Vandierendonck, A. Ramirez, K. De Bosschere and M. Valero A Comparative Study of Redundancy in Trace Caches Proceedings of the 8th International Euro-Par Conference, Vol. 2400, pp. 512-516 (2002)
  50. H. Vandierendonck and K. De Bosschere Evaluation of the Performance of Polynomial Set Index Functions Workshop on Duplicating, Deconstructing and Debunking, held in conjunction with the 29th International Symposium on Computer Architecture, pp. 31-41 (2002)
  51. L. Eeckhout, H. Vandierendonck and K. De Bosschere How Input Data Sets Change Program Behaviour Proceedings of the Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads, held in conjunction with the Eighth International Symposium on High Performance Computer Architecture (HPCA-8), pp. 39-47 (2002)
  52. T. Vander Aa, L. Eeckhout, B. Goeman, H. Vandierendonck, T. Van Achteren, R. Lauwereins and K. De Bosschere Optimizing a 3D Image Reconstruction Algorithm: Investigating the Interaction between the High-Level Implementation, the Compiler and the Architecture Proceedings of the Seventh Asia-Pacific Computer Systems Architecture Conference, Vol. 24(3), pp. 119-126 (2002)
  53. H. Vandierendonck Efficient Evaluation of Randomising Set Index Functions for Cache Memories Second FTW PhD Symposium, pp. (2001)
  54. H. Vandierendonck and K. De Bosschere Efficient Profile-Based Evaluation of Randomising Set Index Functions for Cache Memories Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 120-127 (2001)
  55. L. Eeckhout, T. Vander Aa, B. Goeman, H. Vandierendonck, R. Lauwereins and K. De Bosschere Application Domains for Fixed-Length Block Structured Architectures Proceedings of the 6th Australasian Computer Systems Architecture Conference ACSAC 2001, Vol. 23(4), pp. 35-44 (2001)
  56. B. Goeman, H. Vandierendonck and K. De Bosschere Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency Proceedings of the 7th International Symposium on High-Performance Computer Architecture, pp. 207-216 (2001)
  57. H. Vandierendonck Multi-Module Caches to Improve Cache Hit Ratios First FTW PhD Symposium, pp. (2000)
  58. H. Vandierendonck and K. De Bosschere An Optimal Replacement Policy for Balancing Multi-Module Caches Proceedings of the 12th Symposium on Computer Architecture and High Performance Computing, pp. 65-72 (2000)
  59. H. Vandierendonck and K. De Bosschere A Comparison of Locality-Based and Recency-Based Replacement Policies Proceedings of the 3rd International Symposium on High-Performance Computing, Vol. 1940, pp. 310-318 (2000)
  60. H. Vandierendonck and K. De Bosschere On multi-module caches: replacement policies and organization Parallel Architectures: Design and Exploration, pp. 21-38 (2000)
  61. H. Neefs, H. Vandierendonck and K. De Bosschere A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks Proceedings of the 6th International Symposium on High-Performance Computer Architecture, pp. 313-324 (2000)

Other publications

  1. Hans Vandierendonck and Tom Mens Averting the next software crisis COMPUTER, Vol. 44(4) pp. 88-90 (2011)
  2. Hans Vandierendonck and Andr�� Seznec Managing SMT Resource Usage through Speculative Instruction Window Weighting Rapports de recherche - INRIA, Vol. 7103 pp. 22 (2009)
  3. H. Vandierendonck, V. Desmet and K. De Bosschere Behavior-Based Branch Prediction by Dynamically Clustering Branch Instructions pp. 28 (2006)
  4. Bavo Nootaert, Hans Vandierendonck and Koen De Bosschere A tool for link-time register reallocation and reassignment pp. (2006)
  5. Hans Vandierendonck Improving the YAGS Branch Predictor (003) pp. 1-16 (2005)
  6. Hans Vandierendonck Vermijding van afbeeldingsconflicten in microprocessors Doctoraatsproefschrift Faculteit Toegepaste Wetenschappen, Universiteit Gent, pp. (2004)
  7. H. Vandierendonck and K. De Bosschere On Null Spaces and Their Application to Model Randomisation and Interleaving in Cache Memories (DG 02-02) pp. 29 (2002)
  8. H. Vandierendonck A Comparative Study of Multi-module Caches and Replacement Policies ELIS Technical Report, (DG00-02) pp. 1-36 (2000)
  9. H. Vandierendonck Studie van bankvoorspelling in meerbankscaches Afstudeerwerk FTW, RUG, pp. (1999)