DFR'11

Full Title: 
The 3rd Workshop on Design for Reliability
Event Date: 
Sun, 2011-01-23
Part of: 
HiPEAC 2011
Important dates
Abstract submission date: 
Fri, 2010-10-22
Paper submission date: 
Mon, 2010-11-01
Notification date: 
Fri, 2010-12-03
Final version: 
Fri, 2010-12-10
Motivation:
To stimulate interest in an emerging and challenging issue by bringing
together researchers from various areas (design, verification, test,
architecture, fault-tolerance and reliability) to share ideas and ferment
future research in holistic approaches for reliable next-generation
computing systems.

Scope: 
While technology is scaling well into the nanometer era, design of reliable,
dependable and verifiable systems emerges as one of the most prominent
design challenges. The increasing rate of intermittent and permanent faults
due to design errors, device variability and manufacturing defects
(including wear-outs), environmental impact and aging of devices
(degradation) rises significantly as device size and power supply voltage
shrink. Process variation also shifts the traditional deterministic design
methodology towards a more stochastic and unorthodox design paradigm. The
increased design complexity, increased device parameter variations due to
manufacturing and lithographic defects, reduced noise margins resulting from
the power supply voltage reduction, and the increase of noise due to
crosstalk and power supply, all call for a design environment where
traditional design methodologies are no longer effective. These cause
further challenges in completing design verification and manufacturing
tests; such effects manifest as inherent unreliability of the components,
redefining the design and test paradigm for next-generation computing
systems. Additionally, energy reduction and performance enhancement
techniques force designs to run near zero margins, and factors which cannot
be controlled such as soft errors, thermal impact and aging result in an
increased occurrence of transient and hard faults in computing systems. 

Topics of interest include, but are not limited to:

.	Dependable systems from unreliable components, lifelong reliability
.	Fault-tolerant micro-architectures and system architectures
.	Testing and verification strategies for the future
.	On-line (dynamic) testing and verification techniques
.	Software-based methodologies for fault tolerance and testing
.	System validation mechanisms
.	Built-in self diagnosis, self-tuning and recovery schemes
.	Self-adaptive systems
.	System-level design and integration for reliability, verifiability
and dependability
.	Error modeling, detection, correction, and tolerance for transient
and permanent errors
.	Reliable on-chip communications
.	Energy/reliability/performance tradeoffs
.	Aggressive power saving mechanisms
.	Compiler/architecture/OS methodologies and strategies for
reliability


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Submission guidelines:

Two kinds of papers are invited: (i) technical papers (max. 10 pages) for
relatively mature work, and (ii) position papers (max. 4 pages) on
directions for research and development. Submitted papers should be in the
LNCS format (for manuscript preparation guidelines visit
http://www.springeronline.com/lncs). Papers must be submitted in the PDF
(preferably) or postscript format to the DFR'10 submission website, which
can be found at the workshop's website. Paper and electronic proceedings
with all accepted papers will be distributed at the workshop. 
****************************************************************************


DFR'11 web page: http://www.ece.ucy.ac.cy/labs/easoc/dfr/

-------------------------------
Important dates:
-------------------------------
Abstract Submission Deadline:
October 22nd, 2010

Paper Submission Deadline: 
November 1st, 2010

Notification of acceptance: 
December 3rd, 2010

Camera-ready submission:
December 10th, 2010
------------------------------


Technical Program Committee:

C. Bolchini, Pol. Di Milano, IT
L. Carro, UFRGS, BR
O. Ergin, TOBB, TR
D. Gizopoulos, U. Piraeus, GR
S. Hamdioui, TU Delft, NET
K. Konstantinides, AMD, US
R. Kumar, UIUC, US
S. Kundu, UMass, Amherst, US
M. K. Michael, UCY, CY
H. Naeimi, Intel Corp., US
E. Ozer, ARM, UK
D. Pradhan, U of Bristol, UK
Y. Sazeides, UCY, CY
T. Theocharides, UCY, CY
X. Vera, Intel Corp., SP
H. Wunderlich, ITI Stuttgart, DE
C. Yang, U. of Delaware, US
S. Yehia., Thales, FR


DFR'11 Organizers:

General Chair:
Alex Orailoglu, Univ. of California, San Diego, US alex@cs.ucsd.edu

Program Co-Chairs:

Maria K. Michael, University of Cyprus, CY mmichael@ucy.ac.cy
Yanos Sazeides, University of Cyprus, CY, yanos@cs.ucy.ac.cy
Theocharis Theocharides, University of Cyprus, CY ttheocharides@ucy.ac.cy