.

Publicaties van Peter Verplaetse

Publicaties in tijdschriften

  1. J. Dambre, P. Verplaetse, D. Stroobandt en J. Van Campenhout A Comparison of Various Terminal-Gate Relationships for Interconnect Prediction in VLSI Circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Special Issue on System-Level Interconnect Prediction, Vol. 11(1), pp. 24-34 (2003)
  2. Peter Verplaetse, Dirk Stroobandt en Jan Van Campenhout A stochastic model for the interconnection topology of digital circuits IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 9(6), pp. 938-942 (2001)
  3. P. Verplaetse, D. Stroobandt en J. Van Campenhout A Stochastic Model for the Interconnection Topology of Digital Circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, pp. 938-942 (2001)
  4. D. Stroobandt, P. Verplaetse en J. Van Campenhout Generating Synthetic Benchmark Circuits for Evaluating CAD Tools IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19(9), pp. 1011-1022 (2000)
  5. P. Verplaetse, J. Van Campenhout en H. Neefs ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education IEEE Computer Society Technical Committee on Computer Architecture Newsletter 1999, pp. 57-59 (1999)
  6. P. Verplaetse ESCAPE -- een ontsnappingsroute naar inzicht in moderne microprocessors Persoon en Gemeenschap, Vol. 51(6), pp. 178-187 (1999)

Conferentiepublicaties

  1. J. De Maeyer, H. Devos, W. Meeus, P. Verplaetse en D. Stroobandt Hardware Implementation of an EAN-13 Bar Code Decoder Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 583-584 (2003)
  2. P. Verplaetse, D. Stroobandt en J. Van Campenhout Synthetic Benchmark Circuits for Timing-driven Physical Design Applications Proceedings of the International Conference on VLSI, pp. 31-37 (2002)
  3. M. De Wilde, D. Stroobandt, J. Van Campenhout en P. Verplaetse AQUASUN: adaptive window query processing in CAD applications for physical design and verification Proceedings of the 12th Great Lakes Symposium on VLSI, pp. (2002)
  4. J. Dambre, P. Verplaetse, D. Stroobandt en J. Van Campenhout Getting more out of Donath`s hierarchical model for interconnect prediction Proceedings of the 2002 International Workshop on System Level Interconnect Prediction, pp. 9-16 (2002)
  5. Peter Verplaetse Refinements of Rent's rule allowing accurate interconnect complexity modeling INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, pp. 251-252 (2001)
  6. P. Verplaetse Refinements of Rent`s Rule allowing Accurate Interconnect Complexity Modeling Proceedings of the 2nd International Symposium on Quality Electronic Design, pp. 251-252 (2001)
  7. J. Dambre, P. Verplaetse, D. Stroobandt en J. Van Campenhout On Rent`s Rule for Rectangular Regions Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction, pp. 49-56 (2001)
  8. P. Verplaetse, J. Dambre, D. Stroobandt en J. Van Campenhout On Partitioning vs. Placement Rent Properties Proceedings of the 3nd International Workshop on System-Level Interconnect Prediction, pp. 33-40 (2001)
  9. P. Verplaetse The Interconnect Topology of Digital Circuits First FTW PhD Symposium, pp. CD-ROM (2000)
  10. P. Verplaetse, D. Stroobandt en J. Van Campenhout A Stochastic Model for Interconnection Complexity based on Rent`s Rule Workshop notes of the IEEE International Workshop on Logic Synthesis, pp. 319-325 (2000)
  11. P. Verplaetse, J. Van Campenhout en D. Stroobandt On Synthetic Benchmark Generation Methods Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 213-216 (2000)
  12. F. Habils, P. Verplaetse en J. Van Campenhout Using ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education Software and Hardware Engineering for the 21th Century Proceedings of the 3rd IMACS International Multiconference on: Circuits, Systems, Communications and Computers, pp. 216-222 (1999)
  13. D. Stroobandt, P. Verplaetse en J. Van Campenhout Towards Synthetic Benchmark Circuits for Evaluating Timing-Driven CAD Tools Proceedings of the 1999 International Symposium on Physical Design, pp. 60-66 (1999)
  14. J. Van Campenhout, P. Verplaetse en H. Neefs ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education Workshop on Computer Architecture Education, pp. (1998)

Andere publicaties

  1. Peter Verplaetse Karakterisatie van de Interconnectietopologie van Digitale Schakelingen en Toepassingen in Digitaal Ontwerp Doctoraatsproefschrift Faculteit Toegepaste Wetenschappen, Universiteit Gent, pp. 1-254 (2003)
  2. P. Verplaetse Partitioning properties of general graphs pp. (2003)
  3. P. Verplaetse Synthetic Benchmark Circuits for Timing-Driven Physical Design Applications ELIS Technical Report, (DG 01-03) pp. 1-13 (2001)
  4. P. Verplaetse A Stochastic Model for the Interconnection Topology of Digital Circuits ELIS Technical Report, (DG00-07) pp. 1-9 (2000)
  5. P. Verplaetse On the relationship between Rent`s rule and Pareto points ELIS technical report, (DG00-04) pp. 1-17 (2000)
  6. D. Stroobandt, P. Verplaetse en J. Van Campenhout Generating Synthetic Benchmark Circuits for Evaluating CAD Tools ELIS Technical Report, (DG00-01) pp. 1-19 (2000)
  7. P. Verplaetse Architecturale synthese met VHDL van een snelle scanconvector Afstudeerwerk FTW, RUG, pp. (1996)