The International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS) is the premier
event in design, modeling, analysis, and implementation of modern embedded systems, from system-level
analysis and optimization to hardware/software implementation. The conference is a forum for active
discussion of topics of current and future importance to designers and researchers. The program will
bring together the latest in academic and industrial research and development. High-quality original
papers will be accepted for oral presentation followed by interactive poster sessions. CODES+ISSS 2012
is part of the Embedded Systems Week 2012.
Program chairs: Prof. Naehyuck Chang, Seoul National University (email@example.com) and
Prof. Franco Fummi, University of Verona (firstname.lastname@example.org)
* Abstract submission: March 28, 2012
* Full paper submission: April 04, 2012
* Notification of acceptance: July 03, 2012
* Camera-ready version: July 31, 2012
* Conference: October 7-12, 2012 (Tampere, Finland)
Areas of Interest
The CODES+ISSS invites papers on the specification, modeling, design, analysis, and implementation
designs from embedded systems to systems of systems. The conference covers range of design problems
and applications relevant to important embedded system quality metrics including performance, cost,
power consumption, reliability, security, usability, and compactness. Each paper is supposed to tackle
new challenges based on new novel and innovative idea and/or emerging technologies. The following area
of topics are welcomed but not limited to:
Track 1) Hardware/software co-design - Specification and refinement, design representation, system
synthesis, partitioning, hardware-software interaction/interface, design space exploration,
reconfigurable design, and model-based design.
Track 2) Domain and application-specific design techniques - Analysis, design, and automation techniques
for multimedia, medical, automotive, security, and other specialized application domains.
Track 3) Embedded software - Compilers, memory management, virtual machines, scheduling, operating systems,
real-time support, fault-tolerance, and middleware.
Track 4) Embedded systems architecture - Architecture and micro-architecture design, exploration and
optimization including application-specific, storage systems, memory and communication.
Track 5) Large-scale system architecture - Multi-core, GPU, heterogeneous systems, system-level
communication, and networks-on-chip architectures.
Track 6) Systems of systems - Design and optimization of data centers, cloud computing, heterogeneous
embedded systems, cyber-physical systems, etc.
Track 7) Simulation, validation and verification - Hardware/software co-simulation, verification and
validation methodologies, formal verification, hardware-accelerated simulation, test methodology,
design for testability, specification languages/models, and benchmarks.
Track 8) Power-aware systems - Power- and energy-aware system design and methodologies ranging from
low-power embedded systems to energy-efficient large scale systems such as Green IT and Smart Grid.
Track 9) Industrial practices and case studies - Practical impacts on current and/or future industries
with applications of the state-of-the-art methodologies and tools in various application
areas including wireless, networking, multimedia, automotive, medical systems, sensor networks, etc.
* Papers should represent original work, not published or submitted for publication in other forums.
* A blind review process will be enforced. Authors should not reveal authorship directly or indirectly
* Papers must be in PDF format and should not exceed 10 pages in ACM two-column format (9pt on 8.5"x11"
letter size paper). For formatting instructions and templates, visit the ACM web site. 10 pages is
an upper limit. Authors are encouraged to submit shorter (e.g., 6 pages) papers if this better fits
the nature and content of the paper.
* Formal proceedings will be published on CD-ROM and web page forms (copyright by ACM and IEEE).