Chip performance is currently dominated by interconnects. Not only delay, but also chip area, number of wiring layers (and hence mask cost), power and reliability are mainly determined by the interconnect structure. Therefore, an interconnect-centric chip design methodology is needed. The interconnect performance characteristics are only known after detailed physical design (placement and routing). However, we need a clear picture on these values upfront to make the right design decisions. This requires a predictable interconnect behaviour. In this talk, we present an overview of basic system level interconnect prediction techniques based on Rent`s rule and Donath`s wire length distribution. We also describe some of the recent evolutions that mainly came out of research work presented at the System Level Interconnect Prediction Workshop which is dedicated to this domain. Furthermore, we delve into several applications of interconnect prediction, such as technology extrapolation, layer assignment, yield enhancement, delay prediction, etc.