Abstract��Reservoir Computing (RC) is a computational framework with powerful properties and several interesting advantages compared to conventional techniques for pattern recognition. It consists essentially of two parts: a recurrently connected network of simple interacting nodes (the reservoir), and a readout function that observes the reservoir and computes the actual output of the system. The choice of the nodes that form the reservoir is very broad: spiking neurons [6], threshold logic gates [7] and sigmoidal neurons [5], [9] have been used. For this article, we will use analogue neurons to build an RC-system on a Field Programmable Gate Array (FPGA), which is a chip that can be reconfigured. A traditional neuron calculates a weighted sum of its inputs, which is then fed through a non-linearity (like a threshold or sigmoid function). This is not hardware efficient due to the extensive use of multiplications. In [2], a type of neuron is introduced that communicates using stochastic bitstreams instead of fixed-point values. This drastically simplifies the hardware implementation of arithmetic operations such as addition, the nonlinearity and multiplication. We have built an implementation of RC on FPGA, using these stochastic neurons. In this article we present some results regarding the performance results of this implementation. However, the use of stochastic bitstreams requires some additional precautions. We address some of these challenges and present techniques to overcome them.