Computer architects heavily rely on simulation tools during the design process of their next generation processor. Statistical simulation allows for making quick performance estimates early in the design cycle. However, the current state-of-the-art in statistical simulation still uses microarchitecture-dependent cache models which is impractical when exploring cache hierarchy design spaces. This paper introduces a microarchitecture-independent cache model based on the distributions of the LRU-stack distances and the memory address distances. Preliminary results show that our model is capable of making accurate miss rate predictions.