A Field Programmable Gate Array (FPGA) is a prefabricated digital chip that can be congured to implement an arbitrary digital circuit.
One of the prime advantages of FPGAs compared to Application Specic
Integrated Circuits (ASICs) is the fast turnaround time. As FPGAs become
larger this advantage is under strain, because the compile time grows faster
than the available computer power.
Nowadays, FPGA architectures are optimized for area and performance.
Changing the architecture enables us to trade area and performance for
compilation time. In this paper we examine the inuence of the cluster size
and the wire segment distribution of island style FPGAs on the compilation
time. By compiling a large set of benchmarks for a variety of architectures
we show that the architecture plays an important role in the compilation
speed of FPGAs.