According to Moore??s law the number of transistors on a single chip doubles every 18 months. To respond to this law recent evolutions in computer architecture resulted in multiple processor cores integrated on on a single chip, called a chip multiprocesor (CMP), sharing hardware components such as caches, I/O, etc. Current performance evaluation tools which allow for fast and accurate performance estimation, such as statistical simulation, merely focus on unicore systems. The need rises to extend these methodologies so that they become applicable for chip multiprocessor systems. In this paper we address some extensions that need to be made to statistical simulation so that it is still useful when designing a new CMP.