In a dynamic reordering superscalar processor, the front-endfetches instructions and places them in the issue queue. Instructions arethen issued by the back-end execution core. Till recently, the front-endwas designed to maximize performance without considering energy con-sumption. The front-end fetches instructions as fast as it can until it isstalled by a filled issue queue or some other blocking structure. This ap-proach wastes energy: (i) speculative execution causes many wrong-pathinstructions to be fetched and executed, and (ii) back-end execution rateis usually less than its peak rate, but front-end structures are dimen-sioned to sustained peak performance. Dynamically reducing the front-end instruction rate and the active size of front-end structure (e.g. issuequeue) is a required performance-energy trade-off. Techniques proposedin the literature attack only one of these effects.In previous work, we have proposed Speculative Instruction WindowWeighting (SIWW) [21], a fetch gating technique that allows to addressboth fetch gating and instruction issue queue dynamic sizing. SIWWcomputes a global weight on the set of inflight instructions. This weightdepends on the number and types of inflight instructions (non-branches,high confidence or low confidence branches, ...). The front-end instruc-tion rate can be continuously adapted based on this weight. This paperextends the analysis of SIWW performed in previous work. It shows thatSIWW performs better than previously proposed fetch gating techniquesand that SIWW allows to dynamically adapt the size of the active in-struction queue.