This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to measure a number of important program execution characteristics, to generate a synthetic trace from it, and finally simulate that synthetic trace. The important benefit is that a synthetic trace is very small compared to real program traces.This paper advances statistical simulation to model shared resources, such as shared caches and off-chip bandwidth. This is done (i) by collecting cache set access probabilities and per-set LRU stack depth profiles, and (ii) by modeling a program`s time-varying execution behavior in the synthetic trace. The key benefit is that the statistical profile is independent of the given cache configuration and the amount of multiprocessing which enables statistical simulation to model conflict behavior in shared caches when multiple programs are co-executing on a CMP. We demonstrate that statistical simulation is both accurate and fast with average IPC prediction errors of less than 5.5% and simulation speedups of 40X to 70X compared to the detailed simulation of 100M-instruction traces. This makes statistical simulation a viable tool for CMP design space exploration.