Continuous circuit and wire miniaturization increasingly exert more pressure on the computer designers to address the issue of reliable operation in the presence of hard-faults. Virtually all previous work on hard-fault reliability addresses problems that arise when a fault occurs in architectural resources, such as the register file or caches. However, hard-faults can happen in non-architectural resources, such as prediction arrays and replacement bits. Although these non-architectural hard-faults do not affect correctness they maydegrade a processor performance significantly and, therefore, render them as important to deal with as architectural hard-faults.