High-level synthesis systems overcome the high design effort required to configure an FPGA by trans-lating an algorithm at the behavioral level into a synthesizable hardware description. At this higher level, loop transformations are used to improve the characteristics of the program. These transformations have a great impact on the resulting hardware, but their impact is only known after the execution of all the time-consuming synthesis steps. This hinders a fast design space exploration.In this paper, we tackle this issue by estimating the performance of the hardware loop controller, an often overlooked component in other approaches. We present an equation based model to estimate the area of the loop controller during high-level synthesis. In contrast to other a priori estimation approaches, we manage to keep estimation errors below 8%, which is accurate enough to be useful during design space exploration. Due to its simplicity, theestimation overhead is minimal.