The incorporation of the third dimension in the design of Networks-on-Chip (NoCs) provides a major performance improvement for Chip Multi-Processors (CMPs). Since multicast communication is necessary for parallelization, it is of significant importance to design routing methods that support multicast. The partitioning strategy has a major impact on the efficiency of the multicast routing method. The existing 3D partitioning methods are designed oblivious to the coherent traffic distribution in CMP networks. In this paper, we propose a novel partitioning method which is compatible with the locality of the traffic distribution across the network. By increasing the parallelism through eliminating the unnecessary long paths, a high performance structure is provided which is a valuable asset for CMPs. The experimental results indicate an average gain of 18% in performance and 4% in power consumption near the saturation points by exploiting the proposed partitioning strategy.