Nowadays hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs) commonly replace multi-cores for high-performance applications. FPGAs are hardware accelerators that provide a programmable and massively parallel architecture, but the degree of freedom presents an additional challenge to create efficient designs in a short time span. While high-level synthesis (HLS) tools reduce the implementation effort, the huge design space exploration (DSE) demands a methodology to exploit the FPGA for a particular application in a reasonable time. In order to evaluate the efficiency of FPGAs, a roofline model was adapted to predict the performance and to quantify the impact of the HLS optimisations on the performance overhead. This model will be further fine-tuned and used to guide the design of selected algorithms for high performance execution.