Current High-Level Synthesis (HLS) tools perform excellently for the synthesis of computation kernels, but they often don't optimize memory bandwidth. As memory access is a bottleneck in many algorithms, the performance of the generated circuit will benefit substantially from memory access optimization. In this paper we extend an automated method for detecting and exploiting reuse of array data in loop nests to cases where the loop bounds define a non rectangular iteration domain. In such case, the length of the generated reuse buffers has to change during loop execution according to the varying reuse distance. We make use of the polyhedral representation of the source program, which makes our method computationally easy. Our software complements the existing HLS design flows. Starting from a loop nest written in C, our tool generates the RTL design of a data reuse buffer tailored for the application and a loop controller that streamlines reuse buffer operations with loop body execution, and prepares the loop body for synthesis by an external HLS tool.