Field programmable gate arrays or FPGAs are the Swiss army knife of the compute accelerators. They are highly flexible, have many capabilities, operate at low power and yet have their limitations and are sometimes not easy to handle. In this talk we address the FPGA as an algorithm in hardware and discuss the techniques and tools for efficient hardware-software codesign. After more than two decades of research to raise the abstraction level, high-level synthesis tools now have reached the maturity to be used by the knowledgeable programmer. The architectural views include the OpenCL as well as the C-language with directives oriented paradigms. We will describe the characteristics, parameters and metrics of the logic fabric which are essential to obtain good performance. Next the multiple facets of the design exploration are illustrated with respect to balancing the resources, optimizing the interface and adapting the algorithm for execution on an FPGA. From this discussion we will be able to draw conclusions about the challenges and opportunities for this Swiss army knife accelerator in the arena of high-performance computing.