In this work, we proposed an in-circuit debug methodology. The main parameterised FPGA flow is presented, enhanced with a signal ranking algorithm and parameterised low overhead added infrastructure, for increased design observability. The added infrastructure is optimised alongside the original design and is invoked only when a parameterised trigger is set. The area needed is found by introducing parameterized reconfiguration in the design. Hence, thanks to the fact that there is low over- head over the original implementation, we can incrementally add the debugging functionality almost for free.