Continuous scaling of the semiconductor technology has made the integration of a large number of Intellectual Property (IP) cores into a single chip technically feasible. However, the conventional bus-based and point-to-point interconnects\r\nwhich cannot scale accordingly, have become a principal bottleneck in the design of Multi-Processor Systems-on-Chip (MPSoCs). This has led to a fundamental paradigm shift in the design of interconnections from conventional ad-hoc designs towards modular network-centric approaches that leverage parallelism in order to meet the performance goals. As a result, Networks-on-Chip (NoCs) have emerged as a promising communication approach to address the communication challenges associated with large-scale MPSoCs.\r\nNoCs play a crucial role in the design of high performance parallel processing computing platforms. Given the very different nature of NoCs, the research conducted on off-chip interconnection networks cannot be directly applied to the\r\non-chip domain. NoCs are generally subject to stringent, and often conflicting, timing, power, area, and reliability constraints due to the continuous integration scale. Therefore, the most daunting challenge faced by NoC designers lies in developing solutions to realize the potential benefits offered by NoCs while meeting the above objectives.\r\nThe overall performance of a NoC is strongly affected by the selection of the network topology, routing strategy, and flow control mechanism. The routing method is particularly important as it impacts all network metrics, such as communication latency, throughput, power dissipation, silicon area, Quality of Service (QoS), and reliability. This thesis revolves around the design of efficient routing approaches for NoC-based MPSoC architectures. In particular, the focus of this dissertation is the development of light-weight routing techniques for high-performance NoCs. A promising routing algorithm must strike a balance between the conflicting goals of maximizing performance and reliability as well as minimizing power and area overhead. Thus, we have opted to implement routing mechanisms which do not rely on Virtual Channels (VCs) or routing tables due to the significant time/space overheads typically imposed by them.\r\nWe study and present routing techniques in three major contexts: 2D NoCs, 3D NoCs, and fault-tolerance. In the second part of the thesis which involves 2D NoCs, mesh and torus topology configurations are addressed. For 2D mesh NoCs, we first explore the routing algorithms designed based on the turn model and realize that the adaptivity of the existing methods can still be improved. Based on our findings, we propose the Hamiltonian-based Odd-Even (HOE) turn model \r\nfor both unicast and multicast routing in wormhole-switched 2D mesh networks. HOE is able to maximize the degree of adaptiveness by minimizing the number of prohibited turns, such that the algorithm remains deadlock-free without adding VCs.\r\nMaintaining deadlock-freedom is even more challenging in tori due to the intra-dimensional dependencies caused by the wraparound links. Theoretically, at least two VCs per physical channel are required in a wormhole-switched 2D torus to ensure deadlock-freedom and provide adaptive routing. However, VCs increase the arbitration latency and consume large power/area overheads which is undesirable, particularly for on-chip networks with limited power/area budgets. To address this issue, we introduce a new technique by a proper selection of the routing algorithm and flow control mechanism. By the incorporation of the Abacus Turn Model (AbTM) into the Worm-Bubble Flow Control (WBFC), not only deadlock-free routing is supported for VC-less tori, but also the network blocking is reduced by providing on-demand routing adaptiveness through reconfiguration. \r\nThe third part of the thesis focuses on 3D