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Publications of H Neefs

Journal papers

  1. L. Eeckhout, H. Neefs and K. De Bosschere Early design stage exploration of fixed-length block structured architectures Journal of Systems Architecture, Vol. 46(15), pp. 1469-1486 (2000)
  2. H. Neefs, K. De Bosschere and J. Van Campenhout Exploitable levels of ILP in future processors Journal of Systems Architecture, Vol. 45(9), pp. 687-708 (1999)
  3. P. Verplaetse, J. Van Campenhout and H. Neefs ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education IEEE Computer Society Technical Committee on Computer Architecture Newsletter 1999, pp. 57-59 (1999)

Conference publications

  1. L. Eeckhout, K. De Bosschere and H. Neefs Performance Analysis through Synthetic Trace Generation Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 1-6 (2000)
  2. F. Habils, H. Neefs and K. De Bosschere Designing a Branch Predictor for a Block Structured Architecture Proceedings of the 5th International Conference on Computer Science and Informatics, pp. 683-686 (2000)
  3. L. Eeckhout, K. De Bosschere and H. Neefs On the Feasibility of Fixed-Length Block Structured Architectures Proceedings of the 5th Australasian Computer Architecture Conference ACAC 2000, Vol. 22(4), pp. 17-25 (2000)
  4. B. Goeman, H. Neefs and K. De Bosschere Increasing the Efficiency of Value Prediction in Future Processors by Predicting Less Parallel Computing: Fundamentals and Applications ; Proceedings of the International Conference ParCo99, pp. 518-525 (2000)
  5. L. Eeckhout, H. Neefs and K. De Bosschere Estimating IPC of a Block Structured Instruction Set Architecture in an Early Design Stage Parallel Computing: Fundamentals and Applications ; Proceedings of the International Conference ParCo 99, pp. 468-475 (2000)
  6. H. Neefs, H. Vandierendonck and K. De Bosschere A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks Proceedings of the 6th International Symposium on High-Performance Computer Architecture, pp. 313-324 (2000)
  7. L. Eeckhout, H. Neefs, K. De Bosschere and J. Van Campenhout Investigating the Implementation of a Block Structured Processor Architecture in an Early Design Stage Proceedings of the 25th EUROMICRO Conference, Vol. 1, pp. 186-193 (1999)
  8. B. Goeman, K. De Bosschere and H. Neefs Developing a simulation platform for an experimental architecture Software and Hardware Engineering for the 21th Century Proceedings of the 3rd IMACS International Multiconference on: Circuits, Systems, Communications and Computers, pp. 158-165 (1999)
  9. L. Eeckhout, H. Neefs, K. De Bosschere and J. Van Campenhout On the Organization and Implementation of a Fixed-Length Block Structured Instruction Set Architecture Proceedings of the 1999 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 77-82 (1999)
  10. F. Habils, H. Neefs and K. De Bosschere Branch Prediction, the Old and the New High Performance Computing: Biomedical Applications and Parallel Architectures Proceedings of an international seminar, pp. 49-62 (1999)
  11. B. Goeman, H. Neefs and K. De Bosschere Increasing the ILP through value prediction High Performance Computing: Biomedical Applications and Parallel Architectures, pp. 35-47 (1999)
  12. L. Eeckhout, H. Neefs and K. De Bosschere On the Benefits of a Block Structured Instruction Set Architecture Proceedings of an International Seminar on High Performance Computing: Biomedical Applications and Parallel Architectures, pp. 25-34 (1999)
  13. L. Eeckhout, H. Neefs, K. De Bosschere and J. Van Campenhout Improving Loop Performance on a Block Structured Architecture through Predication Proceedings of the Tenth IASTED International Conference PARALLEL AND DISTRIBUTED COMPUTING AND SYSTEMS, pp. 457-462 (1998)
  14. J. Van Campenhout, P. Verplaetse and H. Neefs ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education Workshop on Computer Architecture Education, pp. (1998)
  15. H. Van Marck, M. Brunfaut, J. Dambre, H. Neefs and J. Van Campenhout Design issues for three-dimensional optoelectronic architectures Proceedings of PIERS 98, Vol. 3, pp. 1064 (1998)
  16. H. Neefs, P. Van Heuven and J. Van Campenhout Latency Requirements of Optical Interconnects at Different Memory Hierarchy Levels of a Computer System Proceedings of Optics in Computing, Vol. 3490, pp. 552-555 (1998)
  17. H. Neefs, P. Van Heuven and J. Van Campenhout Optical Interconnects at the L2 Cache to Main Memory Level in a Computer System and the Effect of Prefetching Proceedings of the International Conference on Telecommunications, Vol. 3, pp. 250-254 (1998)
  18. H. Neefs, P. Van Heuven and J. Van Campenhout A Quantitative Study of Optical Interconnects at the L2-cache to Main Memory Level in a Uniprocessor Workshop notes of the Ninth Annual Workshop on Interconnections Within High Speed Digital Systems, pp. (1998)
  19. L. Eeckhout, H. Neefs, K. De Bosschere and J. Van Campenhout Aspects of a Fixed-Length Block Structured Instruction Set to Improve Loop Performance Proceedings of the international seminar on Software for Parallel Computing: Programming Paradigms, Development Environments and Debugging, pp. 39-55 (1998)
  20. H. Neefs, K. De Bosschere and J. Van Campenhout An Analytical Model for Performance Estimation of Modern Data-Flow Style Scheduling Microprocessors Proceedings of the 22nd Euromicro Conference Beyond 2000: Hardware/Software Design Strategies; Short Contributions, Sept 2-5 1996, pp. 2-7 (1997)
  21. H. Neefs, K. De Bosschere and J. Van Campenhout Microarchitectural Issues of a Fixed Length Block Structured Instruction Set Architecture Proceedings of the 22nd Euromicro Conference Beyond 2000: Hardware/Software Design Strategies; Short Contributions, pp. 8-13 (1997)
  22. H. Neefs, K. De Bosschere and J. Van Campenhout Issues in Compilation for Fixed-Length Block Structured Instruction Set Architectures Proceedings of the Workshop on Interaction between Compilers and Computer Architectures, pp. 1-8 (1997)
  23. H. Neefs and J.M. Van Campenhout A Microarchitecture for a fixed length Block Structured instruction set Architecture Proceedings of the Eighth IASTED International Conference on Parallel and Distibuted Computing and Systems, pp. 38-42 (1996)
  24. H. Neefs, K. De Bosschere and J. Van Campenhout A C++ Simulator modelling a modern data-flow scheduling Microprocessor Syllabus of the Parallel Computing Seminar, pp. 93-100 (1996)
  25. H. Neefs, K. De Bosschere and J. Van Campenhout Simulating a Modern Data-flow Scheduling Microprocessor in C++ Proceedings of an international seminar: Parallel Computing: Software, Architectures and Operating Systems, pp. 100-111 (1996)
  26. J. Depreitere, H. Neefs, H. Van Marck and J. Van Campenhout A Hybrid Optoelectronic 3-D Field Programmable Gate Array demonstrator Symposium on Field-Programmable Gate Arrays, pp. (1995)
  27. Jo Depreitere, Henk Neefs, Herwig Van Marck, Jan Van Campenhout, Roel Baets, Bart Dhoedt, Hugo Thienpont and I VERETENNICOFF A Optoelectronic 3-D Field Programmable Gate Arra. Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications, Springer Verlag, Vol. LNCS 849, pp. 352-360, Prague, 1994. , pp. (1994)
  28. B. Dhoedt, P. De Dobbelaere, J. Blondelle, P. Van Daele, P. Demeester, H. Neefs, J. Van Campenhout and R. Baets Arrays of lightemitting diodes with integrated diffractive microlenses for board-to-board optical interconnect applications: design, modelling and experimental assessment CLEO/Europe - European Quantum Electronics Conference `94, pp. (1994)
  29. J. Depreitere, H. Neefs, H. Van Marck, J.M. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont and I. Veretennicoff An Optoelectronic 3-D Field Programmable Gate Array Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications, Vol. LNCS 849, pp. 352 - 360 (1994)

Other publications

  1. H. Neefs Achievements 1996-2000 Optoelectronic interconnects for integrated circuits Advanced Research initiative in microelectronics MEL-ARI OPTO, pp. 86 (2000)
  2. Henk Neefs Latentiebeheersing in Processors - en implicaties op de opportuniteit van optische interconnecties Doctoraatsproefschrift Faculteit Toegepaste Wetenschappen, Universiteit Gent, pp. 1-202 (2000)
  3. J. Van Campenhout, H. Neefs, A. Vander Vorst, G. Torrese, H. Pauwels, R. Vounckx, L. Sheng, R. Baets, T. Coosemans, P. Modak, H. De Pauw, H. Thienpont, P. Vynck and V. Baukens Seminar and IUAP13-meeting : collection of presented slides IUAP13 Photonic Technologies for Advanced Information Systems, pp. (1999)
  4. H. Neefs Optical Interconnects in Monoprocessor Systems ELIS Technical Report, (DG98-09) pp. 1-31 (1998)
  5. H. Neefs A preliminary Study of a Fixed-Length Block-Structured instruction set Architecture ELIS Technical Report Paris 96-07, Vol. 96(96-07) pp. (1996)
  6. F. Jacobs, H. Neefs, Michiel Ronsse, N. Slaats, B. Van Assche and W. Qi Syllabus of the Parallel Computing Seminar pp. 1-130 (1996)
  7. H. Neefs Architectural Support for and Research on Microthreading ELIS Technical Report Paris 95-02, pp. 1-16 (1995)
  8. J. Van Campenhout, A. Van Calster, M. Brunfaut, J. Depreitere, H. Neefs, J. Vanfleteren, H. Van Marck, D. Stroobandt and C. Das Massaal parallelle informatieverwerking op basis van hybried geintegreerde Si VLSI en III-V opto-elektronische componenten Jaarverslag 1994 ( Deel II ) Samenwerkingsproject IMEC - RUG, pp. 1-16 (1994)
  9. J. Van Campenhout, A. Van Calster, M. Brunfaut, J. Depreitere, H. Neefs, J. Vanfleteren, H. Van Marck and C. Das Massaal parallelle informatieverwerking op basis van hybried geintegreerde Si VLSI en III-V opto-elektronische componenten Jaarverslag 1993 ( Deel II ) Samenwerkingsproject IMEC - RUG, pp. 1-13 (1993)