Extended-counting analog-to-digital conversioncombines the accuracy of sigma delta modulation with the speed of algorithmicconversion. In this paper, a double-sampling technique isintroduced for this type of converter. It is based on a variant of thefully floating bilinear integrator. This way, the clock frequencyof the converter is almost halved. An experimental converterwas designed in a 0.6-um CMOS technology for a bandwidth of500 kHz at a 3.3-V supply. In the switched-capacitor implementation,the hardware is extensively reused. This way, the convertercan be realized with only one operational amplifier. On the otherhand, compared to alternative implementations, the amount ofswitches is increased. These are designed carefully in order notto degrade the performance. The converter converts a sample in24 clock cycles and achieves a dynamic range of 87 dB. The peaksignal-to-noise ratio (SNR) and signal-to-noise-plus-distortionratio (SNDR) were measured to be 82 and 81 dB, respectively. Thepower consumption was 28-mW analog and 20-mW digital. The converter core occupies 0.7 mm2 including digital logic.