In mixed-signal designs, substrate coupling of digital circuit noise can severely compromise the behavior of sensitive analog circuits. This session addresses the quantification of localized high-frequency direct substrate distortions, as opposed to the indirect substrate noise caused by power line ringing. Localized substrate distortions gain importance in contemporary high-resistive bulk-type substrates. This session concentrates around an UMC 0.18??m CMOS IC design where substrate noise generation and measurement circuits have been integrated alongside a sensitive optical receiver circuit. Participants will learn how Substrate Noise Analyst (SNA 3.2/SubstrateStorm A3.6b) has been used to obtain accurate substrate noise predictions. Firstly, a substrate technology description is generated using SubstrateStromTCT. Then, the Assura LVS extraction rules file is adapted to emit shapes for n-wells, substrate contacts and device gates. In the Virtuoso Layout Editor, using a Skill script, different net labels are assigned to each bulk contact. The schematic is adapted to make corresponding toplevel pins for each such net label. SubstrateStorm is then used to extract and simplify a 3D RC network between all bulk contacts. When the simplified RC network and the adapted circuit schematic are joined toghether, predicted substrate noise waveforms are obtained through a Spectre simulation. Very good agreement between predicted and actually measured substrate waveforms is demonstrated. It will also be shown that this substrate noise quantification has helped to track down a malignant substrate coupling effect that would otherwise only have shown up as a mysterious performance degradation.