This paper shows that multirate processing in a cascaded discrete-time $DeltaSigma$ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time $DeltaSigma$ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded $\Delta \Sigma$ modulator enables the power efficient implementation of multiple communication standards.