As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more susceptible to faults. Resiliency to device failures is, therefore, a key objective in the design of the Systems-on-Chip (SoCs). This paper seeks to address reliability by presenting a routing algorithm for 2D mesh NoCs. Using the proposed method which is designed based on the Abacus Turn Model (AbTM), the healthy paths can be dynamically configured according to the location of faults and congestion in the network. As a result, not only the functionality of the network is maintained in the vicinity of faults, but also a high performance communication can be provided. The presented technique is an adaptive, distributed, deadlock-free, and congestion-aware routing method which does not require routing tables or virtual channels. The experimental results demonstrate the reliability of NoC against multiple link failures with a small hardware overhead penalty.